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ds000202-dsp0599 1 p roduct s pecification z89223/273/323/373 16-b it d igital s ignal p rocessors with a/d c onverter features operating range ? 5v 10% ? 0c to 70c standard temperature C40c to +85c extended temperature dsp core ? 16-bit fixed point dsp, 24-bit alu and accumulator ? single-cycle multiply and alu operations ? six-level hardware stack ? six data ram pointers and sixteen program memory pointers ? risc processor with 30 instruction types on-chip peripherals ? 4-channel, 8-bit half-flash a/d converter ? serial peripheral interface (spi) ? three general-purpose counter/timers C two pulse width modulators (pwm) C two watch-dog timers (wdt) ? up to 40 bits of i/o ? pll system clock ? three vectored interrupts servicing eight sources ? low power clock modes with wake-up options general description the z893x3 products are high-performance digital signal processors (dsp) with a modified harvard architecture fea- turing separate program and dual data memory banks. the design is optimized for processing power with a minimum of silicon area. the z893x3 16/24-bit architecture accommodates ad- vanced signal processing algorithms. the operating perfor- mance and efficient architecture provide deterministic in- struction execution. compression, filtering, frequency detection, audio, voice detection, speech synthesis, and oth- er vital algorithms can all be implemented. six data ram pointers provide circular buffer capabilities and simultaneous dual operand fetching. three vectored in- terrupts are complemented by a six-level stack. by integrating a high-speed 4-channel, 8-bit a/d, spi, three counter/timers with pwm and wdt support, and up to 40 bits of i/o, the z893x3 family provides a compact low-cost system solution. to support a wide variety of development requirements, the z893x3 dsp product family features the cost-effective z89223/323 with 8 kwords of rom. the z89273/373, an device package rom (kwords) otp (kwords) data ram (words) mips z89223 44-plcc, 44-pqfp 8 512 20 z89273 44-plcc 8 512 20 z89323 64-tqfp, 68-plcc, 80-pqfp 8 512 20 z89373 64-tqfp, 68-plcc, 80-pqfp 8 512 20
z89223/273/323/373 16-bit digital signal processors with a/d converter zilog 2 ds000202-dsp0599 general description (continued) otp version of the z89223/323, is ideal for prototypes and early production builds. throughout this specification, references to the z893x3 de- vice apply equally to the z89223/273/323/373, unless oth- erwise specified. notes: all signals with an overline are active low. for example, in rd/wr , rd is active high and wr is active low. for i/o ports, p1.3 denotes port1 bit 3. pins called nc are no connectionthey do not connect any power, grounds, or signals. power connections follow conventional descriptions: connection circuit device power v cc v dd ground gnd v ss figure 1. z892x3/3x3 functional block diagram data ram1 256x16 shifter xy multiplier p p2:1 p1:1 p0:1 daddr1 ddata1 pdata ddata0 paddr ddata 8 8 816 16 16 16 16 16 16 16 24 16 msb 16 msb 24 16 16 24 24 24 16 msb d0:1?:1 addr gen unit1 8-bit a/d an0 vahi ea2?a0 ed15?d0 ds wait rd/wr port 0 port 1 port 2 an1 an2 an3 valo p1.1 or clkout p1.0 or int2 p1.2 or sdi p1.3 or sdo p1.4 or ss p1.5 or sclk p1.6 or ui0 p1.7 or ui1 8-bit i/o 8-bit i/o 16-bit counter timer 16-bit counter timer, pwm 16-bit counter timer, pwm spi 4 inputs 4 outputs p2.1 or int1 p2.0 or int0 p2.2 or tmo0 p2.3 or tmo1 p2.4 or wait p2.5 or ui2 p2.6 or tmo2 p2.7 p3.7?3.4 p3.3?3.0 16-bit peripheral interface data ram0 256x16 program rom/otp 8192x16 p2:0 p1:0 p0:0 daddr0 8 d0:0?:0 addr gen unit0 program control unit phase locked loop bank switch stack mux alu accumulator halt reset clki clko v agnd lpf dd v ss av cc 24
z89223/273/323/373 zilog 16-bit digital signal processors with a/d converter ds000202-dsp0599 3 external bus and external registers. the following is made to clarify naming conventions used in this specifica- tion. the external bus and external registers are external to the dsp core, and are used to access internal and external peripherals. figure 2. external bus dsp core external register internal peripheral external register external peripheral external register internal peripheral external register external peripheral z893x3 external bus
z89223/273/323/373 16-bit digital signal processors with a/d converter zilog 4 ds000202-dsp0599 pin functions ea2Cea0. external address bus (output, latched). these pins provide the external register address. this address bus is driven during both internal and external accesses. one of up to seven user-defined external registers is selected by the processor for reads or writes. ext7 is always reserved for use by the processor. ed15Ced0. external data bus (input/output). these pins are the data bus for the user-defined external registers, and are shared by port0. these pins are normally tristated, ex- cept when these registers are specified as destination reg- isters in a write instruction to an external peripheral, or when port0 is enabled for output. this bus uses the control signals rd/wr , ds , and wait , and address pins ea2Cea0. ds . data strobe (output). this pin provides the data strobe signal for the ed bus. ds is active for transfers to/from ex- ternal peripherals only. rd/wr . read/write select (output). this pin controls the data direction signal for the external data bus. data is avail- able from the processor on ed15Ced0 when this signal and ds are both low. wait . wait state (input). this pin is sampled at the rising edge of the clock with appropriate setup and hold times. a single wait-state can be generated internally by setting the appropriate bits in the wait state register. the user must drive this line if multiple wait states are required. this pin is shared with port2. clki. clock (input). this pin is the clock circuit input. it can be driven by a signal or connected to a 32 khz crystal. clko. clock (output). this pin is the clock circuit output. it is used for operation with a 32 khz crystal and the pll to generate the system clock. halt . halt state (input). this pin stops program execution. the processor continuously executes nops and the pro- gram counter remains constant while this pin is held low. this pin offers an internal pull-up. reset . reset (input). this pin resets the processor. it push- es the contents of the program counter (pc) onto the stack and then fetches a new pc value from program memory ad- dress 0ffch after the reset signal is released. the status register is set to all zeros. at power-up ram and other reg- isters are undefined, however, they are left unchanged with subsequent resets. reset can be asserted asynchronously. an0Can3. analog inputs (input). these are the analog in- put pins. the analog input signal should be between valo and vahi for accurate conversions. vahi. analog high reference voltage (input). this pin provides the reference for the full scale voltage of the analog input signals. valo. analog low reference voltage (input). this pin provides the reference for the zero voltage of the analog in- put signals. av cc Cagnd. filtered analog power and ground must be provided on separate pins to reduce digital noise in the an- alog circuits. multifunction pins. the z89223/273/323/373 dsp fami- ly offers a user-configurable i/o structure, which means that most of the i/o pins offer dual functions. the function, direction (input or output), and for output, the characteris- tics (push-pull or open drain) are all under user-control, by programming the configuration registers appropriately as described in the i/o ports section. the following share i/o port pins: int0Cint2. external interrupts (input, edge-triggered). these pins provide three of the eight interrupt sources to the interrupt controller. each is programmable to be rising- edge or falling-edge triggered. the other five interrupt sources are from the on-chip peripherals. clkout. system clock (output). this pin provides access to the internal processor clock. sdi. serial data in (input). this pin is the spi serial data input. sdo. serial data out (output). this pin is the spi serial data output. ss. slave select (input). this pin is used in spi slave mode only. ss advises the spi that it is the target of a serial transfer from an external master. sclk. spi clock (output/input). this pin is an output in master mode and an input in slave mode. ui0, ui1. user inputs (input). these general-purpose input pins are directly tested by the conditional branch instruc- tions. they can also be read as bits in the status register. these are asynchronous input signals that require no special clock synchronization. counter/timer0 and counter/timer1 may use either of these pins as input. ui2. user input (input). this pin is the input to counter/timer 2. tmo0/uo0. counter/timer output or user output 0 (out- put). counter/timer 0 and counter/timer 1 can be pro- grammed to provide output on this pin. when user outputs are enabled, and the counter/timer is disabled, this pin pro- vides the complement of status register bit 5.
z89223/273/323/373 zilog 16-bit digital signal processors with a/d converter ds000202-dsp0599 5 tmo1/uo1. counter/timer output or user output 1 (out- put). counter/timer 0 and counter/timer 1 can be pro- grammed to provide output on this pin. when user outputs are enabled, and the counter/timer is disabled, this pin pro- vides the complement of status register bit 6. tmo2. counter/timer 2 output (output). this pin is the output of counter/timer 2 p0.15Cp0.0. port0 (input/output). this is a 16-bit user i/o port. bits can be configured as input or output or globally as open-drain output. when enabled, port0 uses the 16 data lines of the ed bus. the function of these pins can be dy- namically changed by writing to the port0 configuration registers. the high byte can also be configured to port1 as described in the i/o port section. p1.7Cp1.0. port1 (input/output). these pins are port1 in- puts or outputs when not configured for use as special pur- pose peripheral interface. the following eight pin functions preempt use of these pins when enabled. int2, clkout, sdi, sdo, ss, sclk, ui0, ui1. note: these pins are not bonded out on the 44-pin packages. p2.7Cp2.0. port2 (input/output). these pins are port2 in- puts or outputs when not configured as peripheral interfac- es. the following seven pin functions preempt use of p2.6Cp2.0 when enabled. int0, int1, tmo0/uo0, tmo1/uo1, wait , ui2, tmo2. p2.7 does not include a dual function. note: p2.7Cp2.5 are not bonded out on the 44-pin packages. the following port pins are available only on the 80-pin package: p3.7Cp3.4. port3 (output). these pins are port3 outputs. p3.3Cp3.0. port3 (input). these pins are port3 inputs.
z89223/273/323/373 16-bit digital signal processors with a/d converter zilog 6 ds000202-dsp0599 pin configurations figure 3. 44-pin plcc z89223/273 pin con?guration 44-pin plcc 7 8 9 10 11 12 13 14 15 16 17 ed3/p0.3 ed4/p0.4 v ss ed5/p0.5 ed6/p0.6 ed7/p0.7 ed8/p0.8 ed9/p0.9 v ss ed10/p0.10 ed11/p0.11 reset lpf p2.2/tmo0/uo0 clko clki p2.4/w ait ds p2.3/tmo1/uo1 ea2 ea1 ea0 vahi valo agnd an0 an1 an2 an3 p2.1/int1 av cc v dd rd/wr ed15/p0.15 v ss ed14/p0.14 ed13/p0.13 ed12/p0.12 p2.0/int0 v ss ed2/p0.2 ed1/p0.1 ed0/p0.0 v dd 1 28 18 40 6 39 38 37 36 35 34 33 32 31 30 29 20 22 24 26 4 42
z89223/273/323/373 zilog 16-bit digital signal processors with a/d converter ds000202-dsp0599 7 table 1. 44-pin plcc z89223/273 pin description no symbol function direction no symbol function direction 1 p2.0/int0 port 2.0/interrupt 0 input/output 23 an2 a/d input 2 input 2 ed12/p0.12 external data bus/port0 input/output 24 an3 a/d input 3 input 3 ed13/p0.13 external data bus/port0 input/output 25 p2.1/int1 port 2.1/interrupt 1 input/output 4 ed14/p0.14 external data bus/port0 input/output 26 av cc analog power 5v ss ground 27 v dd power supply 6 ed15/p0.15 external data bus/port0 input/output 28 rd/wr r/w external bus output 7 ed3/p0.3 external data bus/port0 input/output 29 ea0 ext address 0 output 8 ed4/p0.4 external data bus/port0 input/output 30 ea1 ext address 1 output 9v ss ground 31 ea2 ext address 2 output 10 ed5/p0.5 external data bus/port0 input/output 32 p2.3/tmo1 port 2.3/timer output 1 input/output 11 ed6/p0.6 external data bus/port0 input/output 33 ds ext data strobe output 12 ed7/p0.7 external data bus/port0 input/output 34 p2.4/w ait port 2.4/wait for ed input/output 13 ed8/p0.8 external data bus/port0 input/output 35 clki clock/crystal in input 14 ed9/p0.9 external data bus/port0 input/output 36 clko clock/crystal out output 15 v ss ground 37 p2.2/tmo0 port 2.2/timer output 0 input/output 16 ed10/p0.10 external data bus/port0 input/output 38 lpf pll low pass filter input 17 ed11/p0.11 external data bus/port0 input/output 39 reset reset input 18 vahi analog high ref. voltage input 40 v dd power 19 valo analog low ref. voltage input 41 ed0/p0.0 external data bus/port0 input/output 20 agnd analog ground 42 ed1/p0.1 external data bus/port0 input/output 21 an0 a/d input 0 input 43 ed2/p0.2 external data bus/port0 input/output 22 an1 a/d input 1 input 44 v s s ground
z89223/273/323/373 16-bit digital signal processors with a/d converter zilog 8 ds000202-dsp0599 pin configurations (continued) figure 4. 44-pin pqfp z89223/273 pin con?guration ed15/p0.15 v ss ed14/p/p0.14 ed13/p0.13 ed12/p0.12 p2.0/int0 v ss ed2/p0.2 ed1/p0.1 ed0/p0.0 v dd vahi valo agnd an0 an1 an2 an3 p2.1/int1 av cc v dd rd/wr ed3/p0.3 ed4/p0.4 v ss ed5/p0.5 ed6/p0.6 ed7/p0.7 ed8/p0.8 ed9/p0.9 v ss ed10/p0.10 ed11/p0.11 reset lpf p2.2/tmo0/uo0 clko clki p2.4/w ait ds p2.3/tmo1/uo1 ea2 ea1 ea0 1 23 33 44-pin pqfp 11 25 27 29 31 9 7 5 3 44 43 42 41 40 39 38 37 36 35 34 12 13 14 15 16 17 18 19 20 21 22
z89223/273/323/373 zilog 16-bit digital signal processors with a/d converter ds000202-dsp0599 9 table 2. 44-pin pqfp z89223/273 pin description no symbol function direction no symbol function direction 1 ed3/p0.3 external data bus/port0 input/output 23 ea0 ext address 0 output 2 ed4/p0.4 external data bus/port0 input/output 24 ea1 ext address 1 output 3v ss ground 25 ea2 ext address 2 output 4 ed5/p0.5 external data bus/port0 input/output 26 p2.3/tmo1 port 2.3/timer output 1 input/output 5 ed6/p0.6 external data bus/port0 input/output 27 ds ext data strobe output 6 ed7/p0.7 external data bus/port0 input/output 28 p2.4/w ait port 2.4/wait for ed input/output 7 ed8/p0.8 external data bus/port0 input/output 29 clki clock/crystal in input 8 ed9/p0.9 external data bus/port0 input/output 30 clko clock/crystal out output 9v ss ground 31 p2.2/tmo0 port 2.2/timer output 0 input/output 10 ed10/p0.10 external data bus/port0 input/output 32 lpf pll low pass filter input 11 ed11/p0.11 external data bus/port0 input/output 33 reset reset input 12 vahi analog high ref. voltage input 34 v dd power supply 13 valo analog low ref. voltage input 35 ed0/p0.0 external data bus/port0 input/output 14 agnd analog ground 36 ed1/p0.1 external data bus/port0 input/output 15 an0 a/d input 0 input 37 ed2/p0.2 external data bus/port0 input/output 16 an1 a/d input 1 input 38 v ss ground 17 an2 a/d input 2 input 39 p2.0/int0 port 2.0/interrupt 0 input/output 18 an3 a/d input 3 input 40 ed12/p0.12 external data bus/port0 input/output 19 p2.1/int1 port 2.1/interrupt 1 input/output 41 ed13/p0.13 external data bus/port0 input/output 20 av cc analog power 42 ed14/p0.14 external data bus/port0 input/output 21 v dd power 43 v s s ground 22 rd/wr r/w exteral output bus 44 ed15/p0.15 external data bus/port0 input/output
z89223/273/323/373 16-bit digital signal processors with a/d converter zilog 10 ds000202-dsp0599 pin configurations (continued) figure 5. 64-pin tqfp z89323/373 pin con?guration 32 30 25 20 17 49 55 60 64 v dd v ss ed0/p0.0 ed1/p0.1 ed2/p0.2 p1.0/int2 v ss p1.1/clkout p1.2/sdi p2.0/int0 ed12/p0.12 ed13/p0.13 v dd ed14/p0.14 v ss ed15/p0.15 rd/wr v dd av cc p2.1/int1 v ss an3 an2 an1 an0 agnd p1.7/ui1 valo p1.6/ui0 v ss vahi ed11/p0.11 ed3/p0.3 ed4/p0.4 v ss v dd ed5/p0.5 p1.3/sdo ed6/p0.6 p1.4/ss ed7/p0.7 p1.5/sclk p2.7 ed8/p0.8 ed9/p0.9 v ss ed10/p0.10 v ss v ss reset lpf p2.5/ui2 p2.2/tmo0/uo0 p2.6/tmo2 clko clki p2.4/ w ait ds p2.3/tmo1/uo1 v dd ea2 ea1 ea0 hal t 1 33 48 64-pin tqfp 16 510 35 40 45
z89223/273/323/373 zilog 16-bit digital signal processors with a/d converter ds000202-dsp0599 11 table 3. 64-pin tqfp z89223/273 pin description no symbol function direction no symbol function direction 1 ed3/p0.3 external data bus/port0 input/output 33 hal t halt execution input 2 ed4/p0.4 external data bus/port0 input/output 34 ea0 ext address 0 output 3v ss ground 35 ea1 ext address 1 output 4v dd power supply 36 ea2 ext address 2 output 5 ed5/p0.5 external data bus/port0 input/output 37 v dd power supply 6 p1.3/sdo port 1.3/serial output input/output 38 p2.3/tmo1 port2.3/timer output 1 input/output 7 ed6/p0.6 external data bus/port0 input/output 39 ds ext data strobe output 8 p1.4/ss port 1.4/slave select input/output 40 p2.4/w ait port 2.4/wait for ed input/output 9 ed7/p0.7 external data bus/port0 input/output 41 clki clock/crystal in input 10 p1.5/sclk port 1.5/serial clock input/output 42 clko clock/crystal out output 11 p2.7 port 2.7 input/output 43 p2.6/tmo2 port 2.6/timer output 2 input/output 12 ed8/p0.8 external data bus/port0 input/output 44 p2.2/tmo0 port 2.2/timer output 0 input/output 13 ed9/p0.9 external data bus/port0 input/output 45 p2.5/ui2 port 2.5/user input 2 input/output 14 v ss ground 46 lpf pll low pass filter input 15 ed10/p0.10 external data bus/port0 input/output 47 reset reset input 16 v ss ground 48 v ss ground 17 ed11/p0.11 external data bus/port0 input/output 49 v dd power supply 18 vahi analog high ref. voltage input 50 v ss ground 19 v ss ground 51 ed0/p0.0 external data bus/port0 input/output 20 p1.6/ui0 port 1.6/user input 0 input/output 52 ed1/p0.1 external data bus/port0 input/output 21 valo analog low ref. voltage input 53 ed2/p0.2 external data bus/port0 input/output 22 p1.7/ui1 port 1.7/user input 1 input/output 54 p1.0/int2 port 1.0/interrupt 2 input/output 23 agnd analog ground 55 v ss ground 24 an0 a/d input 0 input 56 p1.1/clkout port 1.1/clock output input/output 25 an1 a/d input 1 input 57 p1.2/sdi port 1.2/serial input input/output 26 an2 a/d input 2 input 58 p2.0/int0 port 2.0/interrupt 0 input/output 27 an3 a/d input 3 input 59 ed12/p0.12 external data bus/port0 input/output 28 v ss ground 60 ed13/p0.13 external data bus/port0 input/output 29 p2.1/int1 port 2.1/interrupt 1 input/output 61 v dd power supply 30 avcc analog power 62 ed14/p0.14 external data bus/port0 input/output 31 v dd power supply 63 v ss ground 32 rd/wr r/w external bus output 64 ed15/p0.15 external data bus/port0 input/output
z89223/273/323/373 16-bit digital signal processors with a/d converter zilog 12 ds000202-dsp0599 pin configurations (continued) figure 6. 68-pin plcc z89323/373 pin con?guration 60 44 10 26 nc ed3/p0.3 ed4/p0.4 v ss v dd ed5/p0.5 p1.3/sdo ed6/p0.6 p1.4/ss ed7/p0.7 p1.5/sclk p2.7 ed8/p0.8 ed9/p0.9 v ss ed10/p0.10 v ss nc ed15/p0.15 v ss ed14/p0.14 v dd ed13/p0.13 ed12/p0.12 p2.0/int0 p1.2/sdi p1.1/clkout v ss p1.0/int2 ed2/p0.2 ed1/p0.1 ed0/p0.0 v ss v dd 43 27 61 9 68-pin plcc 1 v ss reset lpf p2.5/ui2 p2.2/tmo0/uo0 p2.6/tmo2 clko clki p2.4/w ait ds p2.3/tmo1/uo1 v dd nc ea2 ea1 ea0 hal t ed11/p0.11 v dd vahi v ss p1.6/ui0 valo p1.7/ui1 agnd an0 an1 an2 an3 v ss p2.1/int1 av cc v dd rd/wr
z89223/273/323/373 zilog 16-bit digital signal processors with a/d converter ds000202-dsp0599 13 table 4. 68-pin plcc z89323/373 pin description no symbol function direction no symbol function direction 1 p1.2/sdi port 1.2/serial input input/output 35 an0 a/d input 0 input 2 p2.0/int0 port 2.0/interrupt 0 input/output 36 an1 a/d input 1 input 3 ed12/p0.12 external data bus/port0 input/output 37 an2 a/d input 2 input 4 ed13/p0.13 external data bus/port0 input/output 38 an3 a/d input 3 input 5v dd power supply 39 v ss ground 6 ed14/p0.14 external data bus/port0 input/output 40 p2.1/int1 port 2.1/interrupt 1 input/output 7v ss ground 41 avcc analog power 8 ed15/p0.15 external data bus/port0 input/output 42 v dd power supply 9 nc no connection 43 rd/wr r/w external bus output 10 nc no connection 44 hal t halt execution input 11 ed3/p0.3 external data bus/port0 input/output 45 ea0 ext address 0 output 12 ed4/p0.4 external data bus/port0 input/output 46 ea1 ext address 1 output 13 v ss ground 47 ea2 ext address 2 output 14 v dd power supply 48 nc no connection 15 ed5/p0.5 external data bus/port0 input/output 49 v dd power supply 16 p1.3/sdo port 1.3/serial output input/output 50 p2.3/tmo1 port2.3/timer output 1 input/output 17 ed6/p0.6 external data bus/port0 input/output 51 ds ext data strobe output 18 p1.4/ss port 1.4/slave select input/output 52 p2.4/w ait port 2.4/wait for ed input/output 19 ed7/p0.7 external data bus/port0 input/output 53 clki clock/crystal in input 20 p1.5/sclk port 1.5/serial clock input/output 54 clko clock/crystal out output 21 p2.7 port 2.7 input/output 55 p2.6/tmo2 port 2.6/timer output 2 input/output 22 ed8/p0.8 external data bus/port0 input/output 56 p2.2/tmo0 port 2.2/timer output 0 input/output 23 ed9/p0.9 external data bus/port0 input/output 57 p2.5/ui2 port 2.5/user input 2 input/output 24 v ss ground 58 lpf pll low pass filter input 25 ed10/p0.10 external data bus/port0 input/output 59 reset reset input 26 v ss ground 60 v ss ground 27 ed11/p0.11 external data bus/port0 input/output 61 v dd power supply 28 v dd power supply 62 v ss ground 29 vahi analog high ref. voltage input 63 ed0/p0.0 external data bus/port0 input/output 30 v ss ground 64 ed1/p0.1 external data bus/port0 input/output 31 p1.6/ui0 port 1.6/user input 0 input/output 65 ed2/p0.2 external data bus/port0 input/output 32 valo analog low ref. voltage input 66 p1.0/int2 port 1.0/interrupt 2 input/output 33 p1.7/ui1 port 1.7/user input 1 input/output 67 v ss ground 34 agnd analog ground 68 p1.1/clkout port 1.1/clock output input/output
z89223/273/323/373 16-bit digital signal processors with a/d converter zilog 14 ds000202-dsp0599 pin configurations (continued) figure 7. 80-pin pqfp z89323/373 pin con?guration v ss p30 ed0/p0.0 ed1/p0.1 ed2/p0.2 p1.0/int2 v ss p1.1/clkout p1.2/sdi p2.0/int0 ed12/p0.12 ed13/p0.13 v dd ed14/p0.14 v ss p3.1 v dd av cc p2.1/int1 v ss an3 an2 an1 an0 agnd p1.7/ui1 valo p1.6/ui0 v ss vahi v dd ed11/p0.11 nc ed15/p0.15 nc nc ed3/p0.3 p3.2 ed4/p0.4 v ss v dd ed5/p0.5 p1.3/sdo ed6/p0.6 p14/ss ed7/p0.7 p1.5/sclk p2.7 ed8/p0.8 ed9/p0.9 v ss p3.3 ed10/p0.10 v ss nc p3.4 nc v dd v ss reset p3.7 lpf p2.5/ui2 p2.2/tmo0/uo0 p2.6/tmo2 clko clki p2.4/w ait ds p2.3/tmo1/uo1 v dd nc ea2 ea1 p3.6 ea0 hal t nc p3.5 rd/wr 510152024 60 55 50 45 41 64 80-pin pqfp 1 65 70 75 80 25 30 35 40
z89223/273/323/373 zilog 16-bit digital signal processors with a/d converter ds000202-dsp0599 15 table 5. 80-pin pqfp z89323/373 pin description no symbol function direction no symbol function direction 1 nc no connection 41 rd/wr r/w external bus output 2 ed15/p0.15 external data bus/port0 input/output 42 p3.5 port 3.5 output 3 nc no connection 43 nc no connection 4 nc no connection 44 hal t halt execution input 5 ed3/p0.3 external data bus/port0 input/output 45 ea0 ext address 0 output 6 p3.2 port 3.2 input 46 p3.6 port 3.6 output 7 ed4/p0.4 external data bus/port0 input/output 47 ea1 ext address 1 output 8v ss ground 48 ea2 ext address 2 output 9v dd power supply 49 nc no connection 10 ed5/p0.5 external data bus/port0 input/output 50 v dd power supply 11 p1.3/sdo port 1.3/serial output input/output 51 p2.3/tmo1 port 2.3/timer output 1 input/output 12 ed6/p0.6 external data bus/port0 input/output 52 ds ext data strobe output 13 p1.4/ss port 1.4/slave select input/output 53 p2.4/w ait port 2.4/wait for ed input/output 14 ed7/p0.7 external data bus/port0 input/output 54 clki clock/crystal in input 15 p1.5/sclk port 1.5/serial clock input/output 55 clko clock/crystal out output 16 p2.7 port 2 7 input/output 56 p2.6/tmo2 port 2.6/timer output 2 input/output 17 ed8/p0.8 external data bus/port0 input/output 57 p2.2/tmo0 port 2.2/timer output 0 input/output 18 ed9/p0.9 external data bus/port0 input/output 58 p2.5/ui2 port 2.5/user input 2 input/output 19 v ss ground 59 lpf pll low pass filter input 20 p3.3 port 3 3 input 60 p3.7 port 3.7 output 21 ed10/p0.10 external data bus/port0 input/output 61 reset reset input 22 v ss ground 62 v ss ground 23 nc no connection 63 v dd power supply 24 p3.4 port 3.4 output 64 nc no connection 25 ed11/p0.11 external data bus/port0 input/output 65 v ss ground 26 v dd power supply 66 p3.0 port 3.0 input 27 vahi analog high ref. voltage input 67 ed0/p0.0 external data bus/port0 input/output 28 v ss ground 68 ed1/p0.1 external data bus/port0 input/output 29 p1.6/ui0 port 1 6/user input 0 input/output 69 ed2/p0.2 external data bus/port0 input/output 30 valo analog low ref. voltage input 70 p1.0/int2 port 1.0/interrupt 2 input/output 31 p1.7/ui1 port 1 7/user input 1 input/output 71 v ss ground 32 agnd analog ground 72 p1.1/clkout port 1.1/clock output input/output 33 an0 a/d input 0 input 73 p1.2/sdi port 1.2/serial input input/output 34 an1 a/d input 1 input 74 p2.0/int0 port 2.0/interrupt 0 input/output 35 an2 a/d input 2 input 75 ed12/p0.12 external data bus/port0 input/output 36 an3 a/d input 3 input 76 ed13/p0.13 external data bus/port0 input/output 37 v ss ground 77 v dd power supply 38 p2.1/int1 port 2.1/interrupt 1 input/output 78 ed14/p0.14 external data bus/port0 input/output 39 av cc analog power 79 v ss ground 40 v dd power supply 80 p3.1 port 3.1 input
z89223/273/323/373 16-bit digital signal processors with a/d converter zilog 16 ds000202-dsp0599 absolute maximum ratings stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this rating is a stress rating only; operation of the device at any condition above those indicated in the operational sections of these specifications is not implied. exposure to absolute maximum rating conditions for extended period may affect device reliability. standard test conditions the characteristics listed below apply for standard test con- ditions as noted. all voltages are referenced to ground. pos- itive current flows into the referenced pin. positive current i (+) flows in to the referenced pin. negative current i (e) flows out of the referenced pin. symbol description min max units v cc supply voltage C0.3 7.0 v t stg storage temperature C65 150 c t a ambient operating temperature s device e device 0 C40 70 85 c c figure 8. test load diagram from output under test i (+) i (? 30 pf 9.1 k w 2.1 k w
z89223/273/323/373 zilog 16-bit digital signal processors with a/d converter ds000202-dsp0599 17 dc electrical characteristics table 7. otp version: v dd = 5v 10%, t a = 0c to +70c for s temperature range t a = C40c to +85c for e temperature range, unless otherwise noted; idd measured with peripherals disabled table 6. rom version: v dd = 5v 10%, t a = 0c to +70c for s temperature range t a = C40c to +85c for e temperature range, unless otherwise noted; idd measured with peripherals disabled symbol parameter condition min typical max i ddCpll supply current using pll v dd = 5.0v, 20 mhz 60ma 66ma i ddCecd supply current using external clock direct v dd = 5.0v, 20 mhz 55 ma 61ma i ddCxod supply current using xtal oscillator direct v dd = 5.0v, 32-khz xtal 250 m a 275 m a i ddCdeep supply current during deep sleep v dd = 5.0v, 32khz xtal 175 m a 193 m a v ih input high level 2.7v v il input low level 0.8v i l input leakage -10a 10a v oh output high voltage i oh = C100 a v dd C0.2v i oh = C160 a 2.4v v ol output low voltage i ol = 1.6 ma 0.4v i ol = 2.0 ma 0.5v i fl output floating leakage current -10a 10a symbol parameter condition min typical max i ddCpll supply current using pll v dd = 5.0v, 20 mhz 78ma 86ma i ddCecd supply current using external clock direct v dd = 5.0v, 20 mhz 75ma 83ma i ddCxod supply current using xtal oscillator direct v dd = 5.0v, 32-khz xtal 17ma 19ma i ddCdeep supply current during deep sleep v dd = 5.0v, 32khz xtal 17ma 19ma v ih input high level 2.7v v il input low level 0.8v i l input leakage -10a 10a v oh output high voltage i oh = C100 a v dd C0.2v i oh = C160 a 2.4v v ol output low voltage i ol = 1.6 ma 0.4v i ol = 2.0 ma 0.5v i fl output floating leakage current -10a 10a
z89223/273/323/373 16-bit digital signal processors with a/d converter zilog 18 ds000202-dsp0599 dc electrical characteristics (continued) figure 9. z89373 typical otp current consumption 60 50 40 30 20 10 0 0 5 10 15 20 25 system clock [mhz] i [ma] dd direct clock with vco off pll clock from 32.8khz crystal
z89223/273/323/373 zilog 16-bit digital signal processors with a/d converter ds000202-dsp0599 19 ac electrical characteristics table 8. v dd = 5v 10%, t a = 0c to +70c for s temperature range t a = C40c to +85c for e temperature range, unless otherwise noted symbol parameter min [ns] max [ns] clock tcy clki cycle time for user-supplied clock 50 31250 cpwh clki pulse width high 21 cpwl clki pulse width low 21 tr clki rise time for 20-mhz user-supplied clock 2 tf clki fall time for 20-mhz user-supplied clock 2 external peripheral bus easet ea setup time to ds fall 10 eahold ea hold time from ds rise 4 rwset read/write setup time to ds fall 10 rwhold read/write hold time from ds rise 0 rdset data read setup time to ds rise 15 rdhold data read hold time from ds rise 0 wrvalid data write valid time from ds fall 5 wrhold data write hold time from ds rise 2 reset rrise reset rise time 20 tcy rwidth reset low pulse width 2 tcy interrupt iwidth interrupt pulse width 1tcy halt hwidth halt low pulse width 3 tcy wait state wlat wait latency time from ds fall 7 wdea wait deassert setup time to clkout rise tbd spi sdiCsclk serial data in to serial clock setup time 10 sclkCsdo serial clock to serial data out valid 15 ssCsclk slave select to serial clock setup time 1/2 sclk period ssCsdo slave select to serial data out valid 15 sclkCsdi serial clock to serial data in hold time 10
z89223/273/323/373 16-bit digital signal processors with a/d converter zilog 20 ds000202-dsp0599 8-bit analog/digital converter table 9. av cc Cagnd = 5v 10% t a = 0c to +70c for s temperature range, unless otherwise noted parameter min typ max units integral nonlinearity (inl) 0.5 1 lsb differential nonlinearity (dnl) 0.5 1 lsb zero offset error 2 3 lsb full scale offset error 2 3 lsb valid input signal range valo vahi v input capacitance 33 40 pf conversion time 23 s input impedance 500ksps 100ksps 44ksps 10 48 110 k w k w k w vahi valo + 2.5 av cc v valo agnd av cc e2.5 v vahiCvalo 2.5 av cc v reference ladder resistance vahi to valo 5k w power dissipation 50 85 mw table 10. av cc Cagnd = 5v 10% t a = C40c to +85c for e temperature range, unless otherwise noted parameter min typ max units integral nonlinearity (inl) 1 lsb differential nonlinearity (dnl) 1 lsb zero offset error 3 4 lsb full scale offset error 3 4 lsb valid input signal range valo vahi v input capacitance 33 40 pf conversion time 23 s input impedance 500ksps 100ksps 44ksps 10 48 110 k w k w k w vahi valo + 2.5 av cc v valo agnd av cc e2.5 v vahiCvalo 2.5 av cc v reference ladder resistance vahi to valo 5k w power dissipation 85 mw
z89223/273/323/373 zilog 16-bit digital signal processors with a/d converter ds000202-dsp0599 21 timing diagrams figure 10. clock timing figure 11. read timing figure 12. read timing using w ait pin tcy cpwl cpwh tt rf easet rwset eahold rwhold rdset rdhold data valid address out ds ea(2:0) rd/wr ed(15:0) rdset wdea wlat rdhold valid address out data wait rd/wr ed(15:0) ea(2:0) ds clkout
z89223/273/323/373 16-bit digital signal processors with a/d converter zilog 22 ds000202-dsp0599 timing diagrams (continued) figure 13. write timing figure 14. write timing using wait pin easet rwset eahold rwhold wrvalid wrhold data valid address out ds ea(2:0) rd/wr ed(15:0) wdea wlat easet wrhold wrvalid valid address out data wait rd/wr ed(15:0) ea(2:0) rwhold ds clkout rwset
z89223/273/323/373 zilog 16-bit digital signal processors with a/d converter ds000202-dsp0599 23 figure 15. spi timing (master and slave modes) sdi-sclk setup sclk-sdi hold ss-sdo valid ss-sclk setup valid valid sclk* sdo ss* sdi sclk-sdo valid tri-state *notes: the polarity of sclk and ss are programmable by the user. ss is used in slave mode only. this figure illustrates data transmission on the falling edge of sclk, data reception on the rising edge of sclk, with ss active low (default).
z89223/273/323/373 16-bit digital signal processors with a/d converter zilog 24 ds000202-dsp0599 functional description instruction timing. most instructions are executed in one machine cycle. a multiplication or multiply/accumulate in- struction requires a single cycle. long immediate instruc- tions, and jump or call instructions, are executed in two ma- chine cycles. specific instruction cycle times are described in the instruction description section. multiply/accumulate. the multiplier can perform a 16- bit x 16-bit multiply, or multiply/accumulate, in one ma- chine cycle using the accumulator and/or both the x and y inputs. the multiplier produces a 32-bit result, however, only the 24 most significant bits are saved for the next in- struction or accumulation. for operations on very small numbers where the least significant bits are important, the data should first be scaled to avoid truncation errors. all inputs to the multiplier should be fractional twos-com- plement, 16-bit binary numbers, which places them in the range [C1 to 0.9999695]. the result is in 24 bits, so the range is [C1 to 0.9999999]. if 8000h is loaded into both the x and y registers, the mul- tiplication produces an incorrect result. positive one cannot be represented in fractional notation, and the multiplier ac- tually yields the result 8000h x 8000h = 8000h (C1 x C1 = C1). the user should avoid this case to prevent erroneous results. a shifter between the p register and the multiplier unit output can shift the data by three bits right or no shift. data bus bank switch. there is a switch that connects the x bus to the ddata bus that allows both the x and y reg- isters to be loaded with the same operand for a one cycle squaring operation. the switch is also used to read the x register. alu. the alu features two input ports. one is connected to the output of the 24-bit accumulator. the other input se- lects either the multiplier unit output or the 16-bit ddata bus (left-justified with zeros in the eight lsbs). the alu performs arithmetic, logic, and shift operations. hardware stack. a six-level hardware stack is connected to the ddata bus to hold subroutine return addresses or data. the call instruction pushes pc+2 onto the stack, and the ret instruction pops the contents of the stack to the pc. user inputs and outputs. the z893x3 features three user inputs, ui0, ui1, and ui2. pins ui0 and ui1 are con- nected directly to status register bits s10 and s11, and can be read, or used as a condition code in any conditional in- struction. pins ui0, ui1 and ui2 may also be used to clock the counter/timers. there are two user output bits, uo0 and uo1, which share pins with the timer outputs tmo0 and tmo1 on port2. when the user outputs are enabled, they are the complements of bits s5 and s6 of the status register. figure 16. multiplier block diagram multiplier shift unit multiplier unit output 16 msb p register (24) y register (16) ddata 16 24 xdata 16 *options: no shift 3 bits right x register (16) figure 17. alu block diagram accumulator (24) 16 msb 24 24 ddata multiplier unit output 16 24 24 mux alu
z89223/273/323/373 zilog 16-bit digital signal processors with a/d converter ds000202-dsp0599 25 interrupts. the z893x3 features three user interrupt inputs which can be programmed to be positive or negative edge- triggered. there are five interrupts generated by internal pe- ripherals: the a/d converter, the serial peripheral interface, and the three counter/timers. internally there are three pri- ority levels. the internal signals for interrupt service re- quests are denoted isr0, isr1, and isr2, with isr0 having the highest priority, and isr2 the lowest. the user can pro- gram which interrupt sources are enabled, and which sourc- es are serviced by the highest, middle, and lowest priority service routines. an interrupt is serviced at the end of an instruction execution. two machine cycles are required to enter an interrupt instruction sequence. the pc is pushed onto the stack. the interrupt controller fetches the address of the interrupt service routine from the following locations in program memory: at the end of the interrupt service routine, a ret instruction is used to pop the stack into the pc. the set-interrupt-enable-flag (sief) instruction enables the interrupts. interrupts are automatically disabled when entering an interrupt service routine. before exiting an in- terrupt service routine the sief instruction can be used to reenable interrupts. registers. in addition to the internal registers for process- ing, control, and configuration, the z893x3 offers up to sev- en user-defined 16-bit external registers, ext0Cext6, de- pending on the register bank select value. the external register address space is shared by the z893x3 internal pe- ripherals. selecting banks 0C4 of the ext register assign- ment allows access to/from three to seven of these addresses for general-purpose use. i/o ports. the z893x3 dsp family features a user-config- urable i/o structure. most of the i/o pins include dual func- tions. the counter/timer, serial peripheral interface, and external interrupt enables determine whether a pin is ded- icated to peripheral or i/o port use. port0. a 16-bit user i/o port. bits can be configured as in- put or output or globally as open-drain output. when en- abled, port0 consumes the 16 data lines used by the ed bus. port0 function and ed bus use can be dynamically alter- nated by enabling and disabling port0. port1. a multifunctional 8-bit port. bits can be configured as input or output or globally as open-drain output. port1 also supports int2, clkout, the serial peripheral inter- face, and user inputs 0 and 1. port2. a multifunctional 8-bit port. bits can be configured as input or output or globally as open-drain output. port2 also supports int0 and int1, all three counter/timer out- puts, ed bus, wait , and ui2. port3. port3 is an 8-bit user i/o port with 4 bits of input and 4 bits of output. it is available only on the 80-pin package. external register usage. the external registers ext0Cext6 are accessed using the external address bus ea2Cea0, the external data bus (ed bus) ed15Ced0, and control signals ds , wait , and rd/wr . these provide a convenient data transfer capability with external periph- erals. data transfers can be performed in a single-cycle. an internal wait state generator is provided to accommodate slower external peripherals. a single wait state can be im- plemented through control register bank15/ext3. for ad- ditional wait states, the wait pin can be used. the wait pin is monitored only during execution of a read or write instruction to external peripherals on the ed bus. wait-state generator. an internal wait-state generator is provided to accommodate slow external peripherals. a single wait-state can be implemented through a control register. for additional states, a dedicated pin (wait ) can be held low. the wait pin is monitored only during ex- ecution of a read or write instruction to external peripherals (ed bus). analog to digital converter. the a/d converter is a 4- channel, 8-bit half-flash converter. two external reference voltages provide a scalable input range. the a/d sample rate is determined by a prescaler connected to the system clock. an interrupt is optionally generated at the end of a conversion. the four input channels can be programmed to operate on demand, continuously, or upon an event (timer or interrupt). counter/timers (c/t0 and c/t1). these c/ts are 16-bit with 8-bit prescalers. they also offer the option of being used as pwm generators and include both hardware and software watch-dog capabilities. both c/ts are identical and can be externally or internally clocked. either c/t can drive tmo0 or tmo1. either c/t can drive any of the three interrupt service requests (isr0, isr1, or isr2). counter/timer (c/t2). this c/t is 16-bits, externally or internally clocked, and can drive tmo2 and/or any of the three interrupt service requests (isr0, isr1, or isr2). serial peripheral interface (spi). the serial peripheral interface provides a convenient means of inter-processor and processor-peripheral communication. it offers the ca- pability to transmit and receive simultaneously. the spi is designed to operate in either master or slave mode. device isr0 isr1 isr2 z89223/273/323/373 1fffh 1ffeh 1ffdh
z89223/273/323/373 16-bit digital signal processors with a/d converter zilog 26 ds000202-dsp0599 memory map program memory. programs of up to 8k words can be masked into internal rom (z89323) or programmed into otp (z89373). four locations are dedicated to the vector addresses for the three interrupt service routines (1ffdhC1fffh) and for the starting address following a reset (1ffch). internal rom is mapped from 0000h to 1fffh, and the highest location for program instructions is 1ffbh. internal data ram. all z893x3 family members feature internal 512 x 16-bit data ram organized as two banks of 256 x 16-bit words each (ram0 and ram1). the three ad- dressing modes available to access the data ram are direct addressing, short form direct, and register indirect. the contents of both data ram banks can be read simul- taneously and loaded into the x and y inputs of the multi- plier during a multiply instruction. the addresses for each data ram bank are: 0e255 (0000he00ffh) for ram0 256e511 (0100he01ffh) for ram1 data ram pointers. in register indirect, each data ram bank is addressed by one of three data ram address point- ers: example: pn:b, where n = pointer number = 0, 1, or 2 b = bank = 0 or 1, thus, p0:0, p1:0, p2:0 for ram0 p0:1, p1:1, p2:1 for ram1 in auto-increment, loop-increment, and loop-decrement in- direct addressing, the pointer is automatically modified. the data ram pointers, which may be read or written di- rectly, are 8-bit registers connected to the lower byte of the internal 16-bit ddata bus. program memory pointers. the first 16 locations of each data ram bank can be used as pointers to locations in pro- gram memory. these pointers provide an efficient way to address coefficients. the programmer selects a pointer lo- cation using two bits in the status register and two bits in the operand. at any one time, there are eight usable pointers, four per bank, and the four pointers are in consecutive lo- cations. example: dn:b, where n = pointer number = 0, 1, 2, or 3 b = bank = 0 or 1, thus, d0:0, d1:0, d2:0, d3:0 for ram0 d0:1, d1:1, d2:1, d3:1 for ram1 if s3/s4 = 01 in the status register, then d0:0/d1:0/d2:0/d3:0 refer to register locations 4/5/6/7 in data ram bank 0. figure 18. memory map data memory not used dram1 dram0 01ff 0100 00ff 0000 ffff program memory not used isr0-isr2 vectors reset vector 1fff-d 1ffc 1ffb 0000 ffff fffc or 8 kw 512 words on-chip memory on-chip memory
z89223/273/323/373 zilog 16-bit digital signal processors with a/d converter ds000202-dsp0599 27 registers both external and internal registers are accessed in one ma- chine cycle. the external registers are used to access the on- chip peripherals when they are enabled. the internal registers of the z893x3 are defined below: x and y are two 16-bit input registers for the multiplier. these registers can be utilized as temporary registers when the multiplier is not being used. p holds the result of multiplications and is read-only. a is a 24-bit accumulator. the output of the alu is sent to this register. when 16-bit data is transferred into this reg- ister, it is placed into the 16 msbs and the least significant eight bits are set to zero. only the upper 16 bits are trans- ferred to the destination register when the accumulator is selected as a source register in transfer instructions. pn:b are the pointer registers for accessing data ram where n = 0, 1, or 2, and b = 0 or 1. they can be directly read or written. they point to locations in data ram. pc is the program counter. any instruction which may modify this register requires two clock cycles. sr is the status register. it contains the alu status and pro- cessor control bits. the status register can always be read in its entirety. s15Cs10 are set/reset by hardware and can only be read by software. s9Cs0 control hardware opera- tions and can be written by software. note: ro = read only, rw = read/write. the status register can always be read in its entirety. s15Cs12 are set/reset by the alu after an operation. s11Cs10 are set/reset by the user input pins. if s9 is set and a multiply/shift option is used, the shifter shifts the result three bits right. this feature allows the data to be scaled and prevents overflows. if s8 is set, the hardware clamps at maximum positive or negative values instead of overflowing. s7 enables interrupts. s6Cs5 are user outputs. the complement of the value in the status register appears on bits 2 and 3 of port2 if the user outputs are enabled by writing a 1 to bit 15 of bank 15Cext3, and counter/timer 0 and 1 are disabled. s4Cs3 are the two msbs in the short form direct mode of addressing. s2Cs0 define the ram pointer loop size as indicated in ta- ble 12. register register de?nition x multiplier x input, 16-bits y multiplier y input, 16-bits p multiplier output, 24-bits a accumulator, 24-bits pn:b six data ram pointers, 8-bits each pc program counter, 16-bits sr status register, 16-bits ext0 depends on bank select #, 16-bits ext1 depends on bank select #, 16-bits ext2 depends on bank select #, 16-bits ext3 depends on bank select #, 16-bits ext4 depends on bank select #, 16-bits ext5 depends on bank select #, 16-bits ext6 depends on bank select #, 16-bits ext7 interrupt status/bank select, 16-bits table 11. status register bit functions sr bit function read/write s15 (n) alu negative ro s14 (ov) alu over?ow ro s13 (z) alu zero ro s12 (c) carry ro s11 (ui1) user input 1 ro s10 (ui0) user input 0 ro s9 (sh3) mpy output arithmetically shifted right by three bits r/w s8 (op) over?ow protection r/w s7 (ie) interrupt enable r/w s6 (uo1 ) user output 1 r/w s5 (uo0 ) user output 0 r/w s4Cs3 short form direct bits r/w s2Cs0 (rpl) ram pointer loop size r/w
z89223/273/323/373 16-bit digital signal processors with a/d converter zilog 28 ds000202-dsp0599 registers (continued) the following are not actually registers, but are read or writ- ten in the same way as hardware registers on the chip: bus is a read-only register which, when accessed, returns the contents of the d-bus. bus is used for emulation only. dn:b refers to locations in ram that can be used as a pointer to locations in program memory which is efficient for co- efficient addressing. the programmer decides which loca- tion to choose from two bits in the status register and two bits in the operand. thus, only the lower 16 possible loca- tions in ram can be specified. at any one time, there are eight usable pointers, four per bank, and the four pointers are in consecutive locations in ram. for example, if s3/s4=01 in the status register, then d0:0/d1:0/d2:0/d3:0 refer to register locations 4/5/6/7 in ram bank 0. note that when the data pointers are being written to, a number is ac- tually being loaded to data ram, so they can be used as a limited method for writing to ram. extn are external registers (n = 0 to 6). these are seven 16-bit register addresses provided for mapping internal and external peripherals into the address space of the processor. note that for external peripherals the actual register ram does not exist on the chip, but would exist as part of the ex- ternal device, such as an a/d result latch. the external ad- dress bus, ea2Cea0, the external data bus, ed15Ced0, ds , wait , and rd/wr are used to access external periph- erals. ext7 is used for register bank select, and to program wait states for ext0Cext6, and is not available for accessing an external peripheral. table 12. rpl description s2 s1 s0 loop size 0 0 0 256 0012 0104 0118 10016 10132 11064 1 1 1 128 register register de?nition bus d-bus dn:b eight data pointers extn external register, 16-bit figure 19. status register 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 256 2 4 8 16 32 64 128 "short form direct" bits user output uo1, uo0 (complemented) global interrupt enable overflow protection mpy output arithmetically shifted right by three bits user input ui1,ui0 (read only) carry zero overflow negative ram pointer loop size s7 s6 s5 s4 s3 s2 s1 s0 s15 s14 s13 s12 s11 s10 s9 s8 novz c ui1 ui0 sh3 op ie uo1 uo0 rpl
z89223/273/323/373 zilog 16-bit digital signal processors with a/d converter ds000202-dsp0599 29 bank/ext register assignments there are 16 different banks of ext registers. control of the bank switching is done via the ext7 register. the same ext7 register exists in all banks. banks 0C5 support different combinations of external reg- isters for external peripherals, and external registers for in- ternal (on-chip) peripherals. use the bank that offers the op- timum combination of internal and external registers to support the application. use it as a preferred working bank to minimize bank switching. banks 6C12 only decode ext6 and ext7. do not use ext0C5 for banks 6C12. banks 13C15 are control register banks. these banks are used in the initialization routines and whenever a configu- ration change is required. refer to the sections on i/o ports and peripherals for details. table 13. ext register assignments banks 0C4 bank0 bank1 bank2 bank3 bank4 ext0 user user user user user ext1 user user user user user ext2 user user user user user ext3 spi data user user spi data user ext4 port0 data port0 data user user user ext5 port2Cport1 data port2Cport1 data port3 data user user ext6 a/d_ch0 data a/d_ch1 data a/d_ch2 data a/d_ch3 data user ext7 interrupt status/ bank select interrupt status/ bank select interrupt status/ bank select interrupt status/ bank select interrupt status/ bank select table 14. ext register assignments banks 5C15 bank5 bank6C12 bank13 bank14 bank15 ext0 a/d_ch1 data not de?ned a/d control c/t2 load/read port0 control ext1 a/d_ch2 data not de?ned c/t0 control c/t1 control port1 ctrl/port0 alloc ext2 a/d_ch3 data not de?ned c/t0 load c/t1 load ports 2, 3, & c/t2 control ext3 spi data not de?ned c/t0 counter c/t1 counter wait state control ext4 port0 data not de?ned c/t0 prescaler ld c/t1 prescaler ld spi control ext5 port2Cport1 data not de?ned c/t0 prescaler c/t1 prescaler system clock control ext6 a/d_ch0 data a/d_ch0 data a/d_ch0 data interrupt polarity interrupt allocation ext7 interrupt status/ bank select interrupt status/ bank select interrupt status/ bank select interrupt status/ bank select interrupt status/ bank select
z89223/273/323/373 16-bit digital signal processors with a/d converter zilog 30 ds000202-dsp0599 bank/ext register assignments (continued) interrupt status/bank select register?ext7 following is a description of ext7. it contains both a bank select field and interrupt status bits. bank select field. the four lsbs of ext7 denote which bank is selected as the current working bank. interrupt status bits. these bits can be read to identify which interrupts are pending. a 1 denotes interrupt pend- ing, and a 0 denotes no interrupt. this ability to identify in- terrupts is particularly useful in polled interrupt operation or when servicing isr2, which may come from several sources. note: write 1 to a particular status bit to clear that bit. before exiting an interrupt service routine, the relevant interrupt bit(s) should be cleared. to clear a bit efficiently: ? load the value of ext7 into a register or memory location ? then load that value back into ext7 performing these steps clear all of the interrupts that were pending, but leave the register bank select unchanged. figure 20. ext7 register interrupt status bits bit 4 = a/d finish interrupt bit 5 = spi interrupt bit 6 = timer0 interrupt bit 7 = timer1 interrupt bit 8 = timer2 interrupt bit 9 = int0 (h/w) interrupt bit 10 = int1 (h/w) interrupt bit 11 = int2 (h/w) interrupt bank select 0000 : bank0 0001 : bank1 : : 1111 : bank15 reserved ext 7 reg d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0
z89223/273/323/373 zilog 16-bit digital signal processors with a/d converter ds000202-dsp0599 31 interrupt allocation register ? bank15/ext6 bits 3C0 of the interrupt allocation register define which unique interrupt source the highest priority, and is allocated to isr0 (interrupt service request 0). bits 7C4 of the interrupt allocation register define which unique interrupt source has the second highest priority, and is allocated to isr1 (interrupt service request 1). bits 15C8 of the interrupt allocation register are enable bits for common interrupt sources which have the lowest prior- ity, and are all allocated to isr2 (interrupt service request 2). all the enabled interrupts which are not allocated to isr0 or isr1, are allocated to isr2. when an isr2 interrupt oc- curs, the interrupt service routine must read the interrupt status register in ext7 to determine the source. the in- terrupt status register can be used for polling interrupts. an interrupt that is not selected as a source to isr0, isr1, or isr2, is disabled. figure 21. interrupt allocation register isr0 source (highest priority) d7 d6 d5 d4 d3 d2 d1 d0 d15 d14 d13 d12 d11 d10 d9 d8 bank 15/ext6 0000 = a/d 0001 = spi 0010 = c/t0 0011 = c/t1 0100 = c/t2 0101 = int0 0110 = int1 0111 = int2 1xxx = isr0 disabled isr1 source (medium priority) 0000 = a/d 0001 = spi 0010 = c/t0 0011 = c/t1 0100 = c/t2 0101 = int0 0110 = int1 0111 = int2 1xxx = isr0 disabled isr2 interrupt source (lowest priority) 1 = enable, 0 = disable bit 8 = a/d bit 9 = spi bit 10 = c/t0 bit 11 = c/t1 bit 12 = c/t2 bit 13 = int0 bit 14 = int1 bit 15 = int2
z89223/273/323/373 16-bit digital signal processors with a/d converter zilog 32 ds000202-dsp0599 bank/ext register assignments (continued) interrupt polarity register ? bank14/ext6 the trigger polarities, rising-edge or falling-edge, of all the external interrupts are programmable. wait-state control register?bank15/ext3 the wait-state control register enables the insertion of wait states when the dsp accesses slow peripherals. this register enables the insertion of one wait state on the ed bus, providing 100 ns of access time instead of 50 ns when operating at 20 mhz. when more than one wait state is nec- essary, input pin p2.4/ wait can be used to provide addi- tional wait states. the wait-state register enables the user to specify which ext registers, ext0Cext6, and which operation, read and/or write, require a wait state. ext7 is an internal register, and requires no wait state. figure 22. interrupt polarity register d7 d6 d5 d4 d3 d2 d1 d0 d15 d14 d13 d12 d11 d10 d9 d8 bank 14/ext 6 reg int0 polarity 0 : rising edge (default) 1 : falling edge int1 polarity 0 : rising edge (default) 1 : falling edge int2 polarity 0 : rising edge (default) 1 : falling edge bits [15:3]?reserved figure 23. wait-state control register d7 d6 d5 d4 d3 d2 d1 d0 d15 d14 d13 d12 d11 d10 d9 d8 bank15/ext3 reg wait-state ext6 wait-state ext0 bit14: 0 = disabled wait input pin (default) 1 = enabled p2.4 as wait input pin bit 15: 0 = disabled uo0, uo1 (default) 1 = enable uo0, uo1 wait-state ext5 wait-state ext4 wait-state ext3 wait-state ext2 wait-state ext1 00 = read (nws), write (nws) 01 = read (nws), write (nws) 10 = read (ws), write (ws) 11 = read (ws), write (ws) nws = no wait state ws = one wait state
z89223/273/323/373 zilog 16-bit digital signal processors with a/d converter ds000202-dsp0599 33 i/o ports i/o pin allocation of ports for the different package types is designed to provide configuration flexibility. each port line of ports 0, 1, and 2 can be independently selected as an input or an output. each ports output lines can be glo- bally selected as push-pull or as open-drain outputs table 15. i/o port bit allocations device pins 44-pin plcc, 44-pin pqfp 64-pin tqfp, 68-pin plcc 80-pin pqfp p0 msb ed15Ced8, or p0.15Cp0.8, or p1.7Cp1.0 ed15Ced8, or p0.15Cp0.8 ed15Ced8, or p0.15Cp0.8 p0 lsb ed7Ced0, or p0.7Cp0.0 ed7Ced0, or p0.7Cp0.0 ed7Ced0, or p0.7Cp0.0 p1 p1.7Cp1.0 p1.7Cp1.0 p2 p2.4Cp2.0 p2.7Cp2.0 p2.7Cp2.0 p3 p3.7Cp3.0 figure 24. port 0, 1 and 2 con?guration oen open-drain data out data in pad auto latch r ? 500 k w
z89223/273/323/373 16-bit digital signal processors with a/d converter zilog 34 ds000202-dsp0599 i/o ports (continued) port0?16-bit programmable i/o bank15/ext0 is the port0 direction control register. bank15/ext1 includes specific bits to enable and config- ure port0. the port0 data register is ext4 in banks 0, 1, or 5. figure 25. port 0 control register figure 26. bank15/ext1 register port i/o direction 0 = input (default) 1 = output d7 d6 d5 d4 d3 d2 d1 d0 d15 d14 d13 d12 d11 d10 d9 d8 bank 15/ext 0 reg d7 d6 d5 d4 d3 d2 d1 d0 d15 d14 d13 d12 d11 d10 d9 d8 bank 15/ext1 int2 0 = disabled (default) 1 = enabled int1 0 = disabled (default) 1 = enabled clkout 0 = disabled (default) 1 = enabled port1 outputs 0 = push-pull (default) 1 = open-drain port i/o output bit directions 0 = input (default) 1 = output port0 outputs 0 = push-pull (default) 1 = open-drain allocation of external data (ed) bus/port0 pin s 000 = ed bus 15-0 (default) 001 = pins 15? ? p1.7?1.0, pins 7? ? ed bus 7? 010 = reserved 011 = pins 15? ? p0.15?08, pins 7? ? ed bus 7? 100 = p0.15?0.0 101 = pins 15? ? p1.7?1.0 pins 7? ? p0.7?0.0 110 = reserved 111 = reserved
z89223/273/323/373 zilog 16-bit digital signal processors with a/d converter ds000202-dsp0599 35 port1?8-bit programmable i/o bank15/ext1 is the port1 control register. the msb is the port1 direction control. port1 data is accessed as the lsb of ext5 in banks 0, 1, or 5. the port1 pins can also be mapped to internal functions. when int2, clkout, ui0 and ui1, or the spi are enabled, they use port1 pins. the 44-pin packages do not feature port1 pins, however, port1 and its internal functions can be mapped to the msb of the ed bus/port0 pins. see bits 2C0 of bank15/ext1. table 16. port1 bit function allocation port pin if condition then else p1.0/int2 bank15/ext1 bit 3 = 1 enable int2 int2 p1.0 p1.1/clkout bank15/ext1 bit 5 = 1 enable clkout clkout p1.1 p1.2/sdi bank15/ext4 bit 0 = 1 enable spi sdi p1.2 p1.3/sdo bank15/ext4 bit 0 = 1 enable spi sdo p1.3 p1.4/ss bank15/ext4 bit 0 = 1 enable spi ss p1.4 p1.5/sclk bank15/ext4 bit 0 = 1 enable spi sclk p1.5 p1.6/ui0 bank13/ext1 bits [2,1] = 10, or bank14/ext1 bits [2,1] = 10 enable ui0 ui0 p1.6 p1.7/ui1 bank13/ext1 bits [2,1] = 11, or bank14/ext1 bits [2,1] = 11 enable ui1 ui1 p1.7
z89223/273/323/373 16-bit digital signal processors with a/d converter zilog 36 ds000202-dsp0599 i/o ports (continued) port2?8-bit programmable i/o bank15/ext2 is the port2 control register. the lsb is the port2 direction control. port2 data is accessed as the msb of ext5 in banks 0,1,or 5. the port2 pins can also be mapped to internal functions. when int0, int1, tmo0, tmo1, wait , ui2, or tmo2 are enabled, they use port2 pins. the 44-pin packages do not feature port2 pins p2.7Cp2.5. table 17. port2 bit function allocation port pin if condition then else p2.0/int0 bank15/ext2 bit 9 = 1 enable int0 int0 p2.0 p2.1/int1 bank15/ext1 bit 4 = 1 enable int1 int1 p2.1 p2.2/tmo0 bank13/ext1 bit [6,5] = 10, or bank14/ext1 bit [6,5] = 10 enable tmo0 tmo0 p2.2 p2.3/tmo1 bank13/ext1 bit [6,5] = 11, or bank14/ext1 bit [6,5] = 11 enable tmo1 tmo1 p2.3 p2.4/w ait bank15/ext3 bit 14 = 1 enable w ait w ait p2.4 p2.5/ui2 bank15/ext2 bit 13 = 1 c/t2 clock is ui2 ui2 p2.5 p2.6/tmo2 bank15/ext2 bits 14 = 1 enable tmo2 tmo2 p2.6 p2.7 p2.7 p2.7 figure 27. bank15/ext2 register d7 d6 d5 d4 d3 d2 d1 d0 d15 d14 d13 d12 d11 d10 d9 d8 bank 15/ext2 port2 i/o directions 0 = input (default) 1 = output port3 0 = disabled (default) 1 = enabled int0 0 = disabled (default) 1 = enabled port2 outputs 0 = push-pull (default) 1 = open-drain counter/timer2 0 = disabled (default) 1 = enabled counter/timer2 operation 0 = stopped (default) 1 = counting if d15 = 0, counter/timer2 clock defined by 0 = system clock/2 (default) 1 = ui2 if d15 = 1, counter/timer2 sleep mode wake-up 0 = disabled (default) 1 = enabled tmo2 counter/timer2 clock 0 = disabled (default) 1 = enabled 0 = defined by d13 (default) 1 = clki
z89223/273/323/373 zilog 16-bit digital signal processors with a/d converter ds000202-dsp0599 37 port3?8-bit programmable i/o port3 is an additional i/o port available only in the 80-pin package. p3.3Cp3.0 are inputs and p3.7Cp3.4 are outputs. bit 8 of bank15/ext2 enables and disables port3. the lsb of bank2/ext5 is the port3 data register.
z89223/273/323/373 16-bit digital signal processors with a/d converter zilog 38 ds000202-dsp0599 peripherals analog to digital converter (a/d) the a/d is a 4-channel 8-bit half-flash converter. it uses two reference resistor ladders, one for the upper 5 bits, and another for the lower 3 bits. two external reference voltage input pins, vahi and valo, set the input voltage mea- surement conversion range. the converter is auto-zeroed prior to each sampling period. bank13/ext0 is the a/d control register. the conversion time depends on the system clock frequency and the selection of the a/d prescaler value, bits div2Cdiv0. the clock prescaler can be programmed to de- rive a 2 s conversion time. for example, when deriving the a/d clock from a 20-mhz system clock, the a/d pres- caler value should be set to divide by 40. bits adst1Cadst0 determine one of the following start conversion options: ? writing to the adctl control register ? isr1 ? c/t2 time-out ? c/t0 time-out the start conversion operation may begin at any time. if a conversion is in progress, and a new start conversion signal is received, the conversion in progress will abort, and a new conversion will initiate. bits quad and scan determine one of the following modes of operation: ? one channel is converted four times, with the results se- quentially written to result registers 0, 1, 2 and 3. ? one channel is converted one time, with the respective result register updated. ? four channels are converted one time each, with the re- spective four result registers updated. ? four channels are converted repeatedly, with the respec- tive four result registers constantly updated. when one of the two four-channel modes is selected, the channel specified by csel1Ccsel0 will convert first. the other three channels will convert in sequence. in the se- quence, an0 follows an3. bit adie enables the a/d to generate interrupts at the end of a conversion. bit adit determines whether an interrupt occurs after the first or fourth conversion. to reduce power consumption the a/d can be disabled by clearing the ade bit. though the a/d will function with smaller input signals and reference voltages, the noise and offsets remain constant. the relative error of the converter will increase and the con- version time will also take longer. figure 28. adc architecture internal bus channel select 4x8 result register a/d control register half-flash a/d converter sample and hold 4-channel multiplexer a/d prescaler start converter isr1 c/t0 c/t2 adctl reg. scan quad an0 an1 an2 an3
z89223/273/323/373 zilog 16-bit digital signal processors with a/d converter ds000202-dsp0599 39 ade (bit 15). a 0 disables any a/d conversions or ac- cessing any a/d registers, except writing to the ade bit. a 1 enables all a/d accesses. reserved (bits 14, 13). reserved for future use. adcint (bit 12). the a/d interrupt bit is read-only. the adcint will reset every time this register is written. adit (bit 11). selects when to set the a/d interrupt if in- terrupts are enabled (adie=1). a value of 0 sets the in- terrupt after the first a/d conversion is complete. a value of 1 sets the interrupt after the fourth a/d conversion is complete. adie (bit 10). a/d interrupt enable. a value of 0 dis- ables the a/d interrupt. a value of 1 enables the a/d in- terrupt. there are four a/d result registers. see the ext register assignments for their location in the different banks. figure 29. adctl register (lsb) table 18. a/d prescaler values (bits 7, 6, 5) div2 div1 div0 a/d prescaler (crystal divided by) 000 8 001 16 010 24 011 32 100 40 101 48 110 56 111 64 table 19. operating modes (bits 4, 3) quad scan option 00 convert selected channel 4 times, then stop 01 convert selected channel, then stop. 10 convert 4 channels, then stop. 11 convert 4 channels continuously. table 20. channel select (bits 1, 0) csel1 csel0 channel 0 0 an0 0 1 an1 1 0 an2 1 1 an3 div0 bank13 / ext0 ( l s b ) div1 div2 csel0 csel1 (reserved) scan quad d7 d6 d5 d4 d3 d2 d1 d0 figure 30. adctl register (msb) table 21. start (bits 9, 8) adst1 adst0 option 00 conversion starts when this register is written. 01 conversion starts on int1 per interrupt allocation register 10 conversion starts on c/t2 time-out. 11 conversion starts on c/t0 time-out. adst0 adst1 d15 d14 d13 d12 d11 d10 d9 d8 adie (reserved) bank13/ext0 (msb) ade adcint adit
z89223/273/323/373 16-bit digital signal processors with a/d converter zilog 40 ds000202-dsp0599 peripherals (continued) counter/timers (c/t0 and c/t1) the z893x3 features two 16-bit counter/timers (c/t) that can be independently configured to operate in various modes. each is implemented as a 16-bit load register and a 16-bit down counter. either c/t input can be selected from ui0 or ui1. either c/t output can be directed to tmo0 or tmo1. the c/t clock is a scaled version of the system clock. each c/t features an 8-bit prescaler. the clock rates of the two c/t are independent of each other. the c/ts can be programmed to recognize clock events on the rising edge, the falling edge, or both rising and falling edges of the input signal. outputs on tmo0 or tmo1 can be pro- grammed to occur with either polarity. if either c/t is enabled and an output pin tmo0 or tmo1 is selected, and at the same time user outputs are enabled, the c/t takes precedence, and status register bits 5 or 6 do not affect the state of the selected pin. c/t modes of operation: mode 0square wave output. the c/t is configured to generate a continuous square wave of 50% duty cycle. writing a new value to the tmlr register takes effect at the end of the current cycle, unless tmr is written. mode 1retriggerable one-shot. the c/t is config- ured to generate a single pulse of programmable duration. the pulse may be either logic high or logic low. retrig- gering the one-shot before the end of the pulse causes it to retrigger for a new duration. mode 28-bit pwm. the c/t is configured to generate a pulse-width modulated waveform. the duty cycle ranges from 0C100% (0/256 to 255/256; 8-bits) of a cycle in steps of 1/256 of a cycle. the asserted state of the waveform may be either logic high or logic low. writing a new pulse- width value to the tmlr register takes effect at the end of current cycle, unless tmr is written. mode 316-bit pwm. the c/t is configured to generate a pulse-width modulated waveform. the duty cycle ranges from 0C100% (0/65,536 to 65,535/65,536; 16-bits) of a cy- cle in steps of 1/65,536 of a cycle. the asserted state of the waveform may be either logic high or logic low. writing a new pulse-width value to the tmlr register takes effect at the end of current cycle, unless tmr is written. mode 4finite pulse string generator. the c/t is configured to generate 1 to 65,535 pulses. the output pulses are actually from the timer clock prescaler divided by 2 (tmclk). they are gated to the output until the timer down-counter underflows. mode 5externally clocked one-shot. the c/t is configured to generate an output pulse. the pulse may be either logic high or logic low. it is deasserted when a pro- grammable number of input events (up to 65,535) occur on the input pin, ui0 or ui1. mode 6software watch-dog timer. the c/t is con- figured to generate a hardware reset on time-out, unless retriggered by software. mode 7hardware watch-dog timer. the c/t is con- figured to generate a hardware reset on time-out unless re- triggered by an event on the input pin, ui0 or ui1. mode 8pulse stopwatch. the c/t is configured to measure the time during which its input is asserted. mode 9edge-to-edge stopwatch. the c/t is config- ured to measure the period from one rising (falling) edge to the next rising (falling) edge on the input. mode 10edge counter. the c/t is configured to count a number of input edges (up to 65,535). input edges may be selected as rising or falling or both. mode 11gated edge counter. the c/t is configured to count the number of input edges (up to 65,535) in a time window set by the second timer. edges are counted until the second timer underflows. input edges may be selected as rising, falling, or both. figure 31. counter/timer 0 and 1 block diagram 15 15 8 7 0 ui1 ui0 tplr 0 tmlr tmr tpr timer load register 16-bit down counter 15 0 tmclkout = tmclk (tmr + 1) tmclkin = system clock system clock 8-bit counter prescaler value zeros 80h 1 ? 2 mux mux 2 x (tpr + 1)
z89223/273/323/373 zilog 16-bit digital signal processors with a/d converter ds000202-dsp0599 41 c/t registers each c/t contains a set of five 16-bit registers. bank13 is used to access the registers for c/t0 and bank14 is for the c/t1 registers. all accesses to c/t registers occur with zero wait states. counter/timer control register (bank13,14/ext1). the c/t control register enables/disables the c/t, selects input and output options, and the mode of operation. tmlrload register (bank13,14/ext2). the 16-bit tmlr register holds the value that is loaded into tmr when tmr underflows. tmrcounter register (bank13,14/ext3). tmr is a 16-bit down counter that holds the current c/t value. it can be read like any other ordinary register. however, writing to tmr is different than writing to an ordinary register. a write to tmr causes the contents of tmlr to be written into tmr, causing the c/t to be retriggered. tplrprescaler load register (bank13,14/ext4). the 16-bit tplr register holds the prescaler load value in its lower 8 bits. bit 15 must be written with a 1, and bits 14C8 must be written with 0s. note: if the c/t interrupt is being used, this register must be re- written at the end of the interrupt service routine in order to enable the next interrupt. the number of clock cycles from the beginning of the interrupt service routine to the write must exceed the prescaler load value. figure 32. c/t0 and c/t1 control register d7 d6 d5 d4 d3 d2 d1 d0 d15 d14 d13 d12 d11 d10 d9 d8 bank 13/ext1 (c/t0) and bank14/ext1 (c/t1) input event 00 = falling edge (default) 01 = rising edge 10 = both rising and falling edges 11 = reserved output select 00 = outputs unaffected (default) 01 = reserved 10 = drive tmo0 pin 11 = reserved output polarity 0 = output asserted high on timeout (default) 1 = output asserted low on timeout mode of operation 0000 = square wave output (default) 0001 = retriggerable one-shot 0010 = pwm (8-bit) 0011 = pwm (16-bit) 0100 = finite pulse string generator 0101 = externally-clocked one-shot 0110 = software watch-dog timer 0111 = hardware watch-dog timer 1000 = pulse stopwatch 1001 = edge-to-edge stopwatch 1010 = edge counter 1011 = gated edge counter test mode* 0 = normal operation 1 = factory test mode reserved c/t 0 = disabled (default) 1 = enabled input select 00 = inputs have no effect (default) 01 = reserved 10 = ui0 pin 11 = ui1 pin *note: the user should always program this bit to "0".
z89223/273/323/373 16-bit digital signal processors with a/d converter zilog 42 ds000202-dsp0599 peripherals (continued) tprprescaler register (bank13,14/ext5). tpr is an 8-bit down counter that holds the current prescaler count value. it can be read like any other ordinary register. how- ever, writing to tpr is different than writing to an ordinary register. a write to tpr causes the lower 8-bit contents of tplr to be written into tpr, causing the prescaler to be retriggered. prescaler operation the prescaler section comprises tplr and tpr, followed by a divide-by-two flip-flop. this operation generates a 50 percent duty cycle output, tmclkin. tprs input clock is the system clock. the maximum prescaler output fre- quency is 1/2 the system clock frequency. after tpr is loaded, it decrements at the system clock fre- quency and generates an output to the divide-by-two flip- flop. when the count reaches 0, the tpr counter is reloaded from the lower 8 bits of tplr register. two other events cause a reloading of the tpr counter: 1. writing to tpr 2. reloading tmr, which happens when tmr under- flows, or when tmr is written. note: for c/t modes 8C11, the external input signal on ui0 or ui1 is synchronized with tmclkin before being ap- plied to tmr. the external input signal frequency must be no higher than 1/2 of the tmclkin frequency. figure 33. tmlrload register figure 34. tmrcounter register figure 35. tplrprescaler load register timer reload value bank 13,14/ext2 15 0 timer register bank 13,14/ext3 15 0 prescaler reload value 14 87 zeros 15 0 1 bank 13,14/ext4 figure 36. tprprescaler register 7 tpr 8-bit counter 0 bank 13,14/ext5
z89223/273/323/373 zilog 16-bit digital signal processors with a/d converter ds000202-dsp0599 43 general-purpose counter/timer (c/t2) this versatile16-bit c/t offers multiple uses, including sleep mode wake-up. it can be clocked with the slow 32 khz crystal clock (clki), while the dsp and other pe- ripheral functions operate at a higher frequency generated by the pll. also included is an independent long duration timer. gpt is a 16-bit down counter that holds the current c/t val- ue. it can be read like any other ordinary register. gptl and gpt share the same address, bank14/ext0. a write to gptl reloads gpt, causing the c/t to be retriggered. when c/t2 underflows, it is reloaded with the most recent value written to gptl. if the c/t2 interrupt is enabled, at underflow an interrupt is generated. the counting operation of the counter can be disabled. the c/t clock source can be selected to be clki, ui2, or the system clock divided by 2. when the c/t2 output is enabled, it drives the tmo2 pin. bank 15/ext2 is the control register for c/t2, and for i/o ports 2 and 3. refer to the i/o ports section, page 33, for a description of the i/o port bit allocation. table 22. c/t2 bits d15 and d13 d15 d13 c/t2 clock sleep/wake-up mode 00 sysclk 2 (default) n/a 01 ui2 n/a 10 clki disabled 11 clki enabled figure 37. counter/timer2 block diagram 15 0 tmr tmo2 sleep mode wake-up timer load register 16-bit down counter gpt?ank14/ext0 (read) gptl?ank14/ext0 write 15 0 system clock ui2 clki mux 2 mux
z89223/273/323/373 16-bit digital signal processors with a/d converter zilog 44 ds000202-dsp0599 general-purpose counter/timer (c/t2) (continued) figure 38. counter/timer2 control register d7 d6 d5 d4 d3 d2 d1 d0 d15 d14 d13 d12 d11 d10 d9 d8 bank 15/ext2 port2 i/o directions 0 = input (default) 1 = output port3 0 = disabled (default) 1 = enabled int0 0 = disabled (default) 1 = enabled port2 outputs 0 = push-pull (default) 1 = open-drain counter/timer2 0 = disabled (default) 1 = enabled counter/timer2 operation 0 = stopped (default) 1 = counting if d15 = 0, counter/timer2 clock defined by 0 = system clock/2 (default) 1 = ui2 if d15 = 1, counter/timer2 sleep mode wake-up 0 = disabled (default) 1 = enabled tmo2 counter/timer2 clock 0 = disabled (default) 1 = enabled 0 = defined by d13 (default) 1 = clki
z89223/273/323/373 zilog 16-bit digital signal processors with a/d converter ds000202-dsp0599 45 serial peripheral interface the z893x3 incorporates a serial peripheral interface (spi) for communication with other microcontrollers and periph- erals. the spi can be operated either as the system master, or as a system slave. the spi consists of three registers: the spi control register (bank15/ext4), the spi re- ceive/buffer register (rxbuf), and the spi shift register. spi data access receive operations are double buffered. bank0/ext3 ac- cesses both rxbuf for read (receive) operations, and the spi shift register for write (transmit) operations. spi control register this register is the low byte of bank15/ext4. it is a read/write register that controls master/slave selection, ss polarity, clock source and phase selection, and indicates byte available and data overrun conditions. the control reg- ister is multifunction depending on master/slave mode se- lection. in master mode, bit 6 defines the spi clock source. a 1 selects sclk = c/t0 output, and a 0 selects sclk = sys- tem clock divided down by 2, 4, 8, or 16, as determined by bits 1 and 2. in slave mode, bit 1 is the receive byte overrun flag. this flag can be cleared by writing a 0 to this bit. bit 2 is the sdo output enable.a 0 tristates sdo, a 1 enables data output on sdo. bit 4 signals that a receive byte is available in the rxbuf register. if the associated interrupt enable bit is enabled, an interrupt is generated. master mode operation the dsp must first activate the target slaves select pin through an i/o port. loading data into the spi shift register initiates the transfer. data is transferred out the sdo pin to the slave one data bit per sclk cycle. the msb is shifted out first. at the conclusion of the transfer, the receive byte available flag is set, and if enabled, an spi interrupt is gen- erated. the receive byte available flag is reset when rx- buf is read. figure 39. spi data access d15 d14 bank 0/ext 3 register d7 d6 d5 d4 d3 d2 d1 d0 bits 7e0 spi data (spi shift register for transmit and rxbuf for receive) bit 14 receive character available bit 15 receive character overrun figure 40. spi control register d7 d6 d5 d4 d3 d2 d1 d0 spi enable 0 = disable (default) 1 = enable bank15 / ext4 ( l s b ) receive byte overrun (slave) output enable(slave) 0 = tri-state sdo 1 = enable sdo as output slave select polarity 0 = ss active low (default) 1 = ss active high received byte available sclk polarity 0 = transmit on falling edge, receive on rising edge 1 = transmit on rising edge, receive on falling edge spi clock source select (master) 0 = system clock divided down. 1 = c/t0 mode of operation 1 = master sclk frequency (master) 00 = system clock ? 2 01 = system clock ? 4 10 = system clock ? 8 11 = system clock ? 16 0 = slave
z89223/273/323/373 16-bit digital signal processors with a/d converter zilog 46 ds000202-dsp0599 serial peripheral interface (continued) slave mode operation ss must be asserted to enable a data transfer. incoming data on the sdi pin is shifted into the spi shift register one data bit per sclk cycle. when a byte of data is received, the spi shift register contents are automatically copied into rxbuf. the receive byte available flag is set, and if en- abled, an spi interrupt is generated. the next byte of data may be received at this time. the current byte in rxbuf must be read before the next bytes reception is complete, or the receive byte overrun flag will set, and the data in rxbuf will be overwritten. the receive byte available flag is reset when rxbuf is read. unless the spi output, sdo, is disabled, for every bit that is transferred into the slave through the sdi pin, a bit is transferred out through the sdo pin on the opposite clock edge. during slave operation, sclk is an input. note: slave mode is not available on the 44-pin package. figure 41. spi block diagram spi clock spi counter interrupt spi i/o spi shift register spi receive buffer (rxbuf) spi control (scon) int sclk/p1.5 sdo/p1.3 sdi/p1.2 ss/p1.4 c/t0 system clock (from pll block)
z89223/273/323/373 zilog 16-bit digital signal processors with a/d converter ds000202-dsp0599 47 system clock generator the system clock can be generated from an external clock signal, or from the internal crystal oscillator. for the latter case, a 32-khz crystal is used in conjunction with the in- ternal crystal oscillator. the system clock generator in- cludes a phase-locked loop (pll) circuit to derive a high- frequency system clock from the low-frequency crystal os- cillator. the benefits of using a low-frequency crystal are lower system cost, lower power consumption and lower emi. the z893x3 supports several low-power clock modes to op- timize power consumption. total power consumption de- pends on system clock frequency, and which oscillators and peripherals are enabled. modes of operation the various modes of clock operation are selected by writ- ing to the appropriate bits and fields of the clock control register, bank15/ext5. the mode of operation can be switched dynamically during program execution. power-up and reset (default) at power-up, and following a reset or sleep mode recov- ery, system clock select = 0, therefore system clock = clki. the xtal oscillator is running, so clki may be provided by a crystal, as depicted, or by an external clock (not shown). the vco is running to minimize the time re- quired to switch the system clock to pll out. external clock direct in this mode, an external clock on clki provides the sys- tem clock. clko is not connected. system clock select = 0. the pll is not used. the xtal oscillator and vco are both stopped to reduce power consumption. crystal oscillator direct in this mode of operation, the xtal oscillator is running, and an external crystal provides a 32-khz (typical) clock at clki. system clock select = 0, so the system clock is the frequency at clki (32 khz). this mode requires less power than running at a high-frequency clock rate. the vco may be stopped to conserve even more power, or left running for rapid switching (wake up) to a high-frequency pll generated clock. whenever the pll circuit is enabled, stop vco = 0, and a software delay of 10 ms must be ob- served before switching system clock from clki to pll out. as a result, the pll has time to stabilize. pll clock an external 32-khz crystal, together with the on-chip xtal oscillator, provides the pll input. the vco gen- erates the system clock. a low-pass filter must be connect- ed to lpf as depicted. the xtal oscillator and vco are both running, and system clock = pll out (system clock select = 1). the frequency generated by the pll is deter- figure 42. system clock generator vco 8-bit phase detector stop vco pll out. sel. pll divisor system stop xtal osc lpf 32 khz on-chip off -chip system clock 00 clock divide lpf clki clko clock control register mux mux ? 2 ? 2 ? 2 01 10 11 0 1 xtal osc. pll out clock select pll vco out pll in clki
z89223/273/323/373 16-bit digital signal processors with a/d converter zilog 48 ds000202-dsp0599 system clock generator (continued) mined by the pll divisor value in the msb of the clock control register, bank15/ext5: vco frequency = 4 x pll divisor x pll in frequency. the pll divisor value should be between 1 and156 to ob- tain a vco frequency between 128 khz and 20 mhz from a 32-khz input. there are four options for pll out: vco out, vco out divided by 2, vco out divided by four, or twice the crystal frequency. this selection is determined by the pll out se- lect bits in the clock control register. note: the pll is designed and tested to operate with an input frequency of approximately 32 khz. it is possible to drive the input with a crystal or user-generated clock at some other frequency, but the results are not guaranteed. sleep modes the z893x3 supports various clock modes to minimize de- vice power consumption. the lowest power mode is deep sleep in which the system clock is stopped, and the vco and xtal oscillator are both turned off. wake-up from sleep modes the wake-up trigger source is specified by bits 5 and 6 of the clock control register. the polarity of the wake- up signal is defined by bit 7. wake-up occurs when the wake-up signal is toggled to the specified wake-up polarity. wake-up resumes operation starting from the reset vector address in the same way the chip responds to an external reset . table 23. standard clock mode summary mode clki src stop xtal osc. stop vco sys clk sel power-up/reset (default) xtal, user 000 pll clock xtal 0 0 1 crystal oscillator direct xtal 0 1 0 external clock direct user 1 1 0 deep sleep (lowest power) xtal, user 111 figure 43. system clock control register d7 d6 d5 d4 d3 d2 d1 d0 d15 d14 d13 d12 d11 d10 d9 d8 bank 15/ext 5 reg stop recovery level 0 : low (default setting after reset) 1 : high stop_vco 0 : vco running 1 : stop vco bypass_pll 0 : clock source is oscillator 1 : clock source is vco dsp (system) clock source 00 : vco clock 01 : vco clock divided by 2 10 : vco clock divided by 4 11 : twice the crystal frequency recovery source 00 : por (power-on reset) or port 2, bit 0 (int0) 01 : por or port 1, bit 4 (ss) 10 : por or port 1, bit 6 (ui0) 11 : por or port 2, bit 0 or port 1, bit 4 or port 1, bit 6 programmable pll divider register system clock = bits 15e8 x 4 x crystal frequency (32.768 khz) stop_osc 0 : oscillator running 1 : stop oscillator
z89223/273/323/373 zilog 16-bit digital signal processors with a/d converter ds000202-dsp0599 49 instruction set the addressing modes are: , . these modes are used for loads to and from registers within the chip, such as loading to the accumulator, or loading from a pointer register. the names of the registers are specified in the operand field (destination first, then source). . this mode is used for access to the lower 16 ad- dresses in each bank of ram. the 4-bit address comes from 2 bits of the status register and 2 bits of the operand field of the data pointer. data registers can be used to access data in ram, but typically are used as pointers to access data from the program memory. . similar to the previous mode, the address for the program memory read is stored in the accumulator. hence, @a in the second operand field loads the number in mem- ory specified by the address in a. . the direct mode allows read or write to data ram from the accumulator by specifying the absolute address of the ram in the operand of the instruction. a number be- tween 0 and 255 indicates a location in ram bank 0, and a number between 256 and 511 indicates a location in ram bank 1. . this address mode indicates a long immediate op- erand. a 16-bit word can be loaded directly from the oper- and into the specified register or memory location. . this address mode indicates a short immediate operand. it is used to load 8-bit data into the specified ram pointer. . this mode is used for indirect access to the data ram. the address of the ram location is stored in the pointer. the @ symbol indicates indirect and precedes the pointer. for example, @p1:1 refers to the location in ram bank 1 specified by the value in the pointer. . this mode is used for indirect access to the program memory. the address of the memory is located in a ram location, which is specified by the value in a pointer. therefore, @@p1:1 instructs the processor to read from a location in memory, which is specified by a value in ram, and the location of the ram is in turn specified by the value in the pointer. note: the data pointer can also be used for a memory access in this manner, but only one @ precedes the pointer. in both cases, each time the addressing mode is used, the memory address stored in ram is incremented by one to allow easy transfer of sequential data from program memory. table 24. instruction set addressing modes symbolic name syntax description pn:b pointer registers (points to ram) dn:b data registers x, y, pc, sr, p, edn, a, bus hardware registers (points to program memory) @a accumulator memory indirect direct address expression # long (16-bit) immediate value # short (8-bit) immediate value (points to ram) @pn:b pointer register indirect @pn:b+ pointer register indirect with increment @pn:bCloop pointer register indirect with loop decrement @pn:b+loop pointer register indirect with loop increment (points to program memory) @@pn:b pointer register memory indirect @dn:b data register memory indirect @@pn:bCloop pointer register memory indirect with loop decrement @@pn:b+loop pointer register memory indirect with loop increment @@pn:b+ pointer register memory indirect with increment
z89223/273/323/373 16-bit digital signal processors with a/d converter zilog 50 ds000202-dsp0599 condition codes the following instruction description defines the condition codes supported by the dsp assembler. if the instruction description refers to the (condition code) symbol in one of its addressing modes, the instruction only executes if the condition is true. code description c carry eq equal (same as z) f false ie interrupts enabled mi minus nc no carry ne not equal (same as nz) nie not interrupts enabled nov not over?ow nu0 not user zero nu1 not user one nz not zero ov over?ow pl plus (positive) u0 user zero u1 user one uge unsigned greater than or equal (same as nc) ult unsigned less than (same as c) z zero
z89223/273/323/373 zilog 16-bit digital signal processors with a/d converter ds000202-dsp0599 51 instruction descriptions inst. description synopsis operands words cycles examples abs absolute value abs[,] ,a a 1 1 1 1 abs nc, a abs a add addition add, a, a, a, a, a, a, a, a, 1 1 2 1 1 1 1 1 1 1 2 3 1 1 1 1 add a,p0:0 add a,d0:0 add a,#%1234 add a,@@p0:0 add a,%f2 add a,@p1:1 add a,x add a, #%12 and bitwise and and, a, a, a, a, a, a, a, a, 1 1 2 1 1 1 1 1 1 1 2 3 1 1 1 1 and a,p2:0 and a,d0:1 and a,#%1234 and a,@@p1:0 and a,%2c and a,@p1:2+loop and a,ext3 and a, #%12 call subroutine call call [,]

, 2 2 2 2 call z,sub2 call sub1 ccf clear c ?ag ccf none 1 1 ccf cief clear ie flag cief none 1 1 cief copf clear op ?ag copf none 1 1 copf cp comparison cp, a, a, a, a, a, a, a, a, 1 1 1 1 1 1 2 1 1 1 3 1 1 1 2 1 cp a,p0:0 cp a,d3:1 cp a,@@p0:1 cp a,%ff cp a,@p2:1+ cp a,stack cp a,#%ffcf cp a, #%12 dec decrement dec [,] a, a 1 1 1 1 dec nz,a dec a inc increment inc [,] ,a a 1 1 1 1 inc pl,a inc a jp jump jp [,]

, 2 2 2 2 jp c,label jp label
z89223/273/323/373 16-bit digital signal processors with a/d converter zilog 52 ds000202-dsp0599 instruction descriptions (continued) ld load destination with source ld, a, a, a, a, a, a, ,a , , , , , , , , , , , , 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 1 1 1 1 1 1 1 1 3 1 1 1 1 1 1 1 1 1 2 3 3 1 1 ld a,x ld a,d0:0 ld a,p0:1 ld a,@p1:1 ld a,@d0:0 ld a,124 ld 124,a ld d0:0,ext7 ld p1:1,#%fa ld p1:1,ext1 ld@p1:1,#1234 ld @p1:1+,x ld y,p0:0 ld sr,d0:0 ld pc,#%1234 ld x,@a ld y,@d0:0 ld a,@p0:0Cloop ld x,ext6 notes: when is , cannot be p. when is and is , cannot be extn if is extn, cannot be x if is x, cannot be sr if is sr. when is cannot be a. mld multiply mld , [,] , ,, , ,, 1 1 1 1 1 1 1 1 mld a,@p0:0+loop mld a,@p1:0,off mld @p1:1,@p2:0 mld @p0:1,@p1:0,on notes: if src1 is it must be a bank 1 register. src2s for src1 cannot be x. for the operands , the defaults to off. for the operands , the defaults to on. mpya multiply and add mpya , [,] , ,, , ,, 1 1 1 1 1 1 1 1 mpya a,@p0:0 mpya a,@p1:0,off mpya @p1:1,@p2:0 mpya@p0:1,@p1:0,on notes: if src1 is it must be a bank 1 register. src2s must be a bank 0 register. for src1 cannot be x. for the operands , the defaults to off. for the operands , the defaults to on. mpys multiply and subtract mpys , [,] , ,, , ,, 1 1 1 1 1 1 1 1 mpys a,@p0:0 mpys a,@p1:0,off mpys @p1:1,@p2:0 mpys @p0:1,@p1:0,on inst. description synopsis operands words cycles examples
z89223/273/323/373 zilog 16-bit digital signal processors with a/d converter ds000202-dsp0599 53 notes: if src1 is it must be a bank 1 register. src2s must be a bank 0 register. for src1 cannot be x. for the operands , the defaults to off. for the operands , the defaults to on. neg negate neg ,a , a a 1 1 1 1 neg mi,a neg a nop no operation nop none 1 1 nop or bitwise or or , a, a, a, a, a, a, a, a, 1 1 2 1 1 1 1 1 1 1 2 3 1 1 1 1 or a,p0:1 or a, d0:1 or a,#%2c21 or a,@@p2:1+ or a, %2c or a,@p1:0Cloop or a,ext6 or a,#%12 pop pop value from stack pop 1 1 1 1 1 1 1 1 pop p0:0 pop d0:1 pop @p0:0 pop a push push value onto stack push 1 1 1 1 2 1 1 1 1 1 1 2 3 3 push p0:0 push d0:1 push @p0:0 push bus push #12345 push @a push @@p0:0 ret return from subroutine ret none 1 2 ret rl rotate left rl ,a ,a a 1 1 1 1 rl nz,a rl a rr rotate right rr ,a ,a a 1 1 1 1 rr c,a rr a scf set c ?ag scf none 1 1 scf sief set ie ?ag sief none 1 1 sief sll shift left logical sll [,]a a 1 1 1 1 sll nz,a sll a sopf set op ?ag sopf none 1 1 sopf sra shift right arithmetic sra,a ,a a 1 1 1 1 sra nz,a sra a sub subtract sub, a, a, a, a, a, a, a, a, 1 1 2 1 1 1 1 1 1 1 2 3 1 1 1 1 sub a,p1:1 sub a,d0:1 sub a,#%2c2c sub a,@d0:1 sub a,%15 sub a,@p2:0Cloop sub a,stack sub a, #%12 inst. description synopsis operands words cycles examples
z89223/273/323/373 16-bit digital signal processors with a/d converter zilog 54 ds000202-dsp0599 instruction descriptions (continued) bank switch operand. the third (optional) operand of the mld, mpya and mpys instructions represents wheth- er the bank switch is set to on or off. to illustrate, the keywords on and off are used to state the direction of the switch. these keywords are referenced in the instruction de- scriptions through the symbol. the most no- table capability is that a source operand can be multiplied by itself (squared). xor bitwise exclusive or xor , a, a, a, a, a, a, a, a, 1 1 2 1 1 1 1 1 1 1 2 3 1 1 1 1 xor a,p2:0 xor a,d0:1 xor a,#13933 xor a,@@p2:1+ xor a,%2f xor a,@p2:0 xor a,bus xor a, #%12 inst. description synopsis operands words cycles examples
z89223/273/323/373 zilog 16-bit digital signal processors with a/d converter ds000202-dsp0599 55 package information figure 44. 44-pin plcc package diagram figure 45. 44-pin pqfp package diagram
z89223/273/323/373 16-bit digital signal processors with a/d converter zilog 56 ds000202-dsp0599 package information (continued) figure 46. 64-pin tqfp package diagram
z89223/273/323/373 zilog 16-bit digital signal processors with a/d converter ds000202-dsp0599 57 figure 47. 68-pin plcc package diagram
z89223/273/323/373 16-bit digital signal processors with a/d converter zilog 58 ds000202-dsp0599 package information (continued) figure 48. 80-pin pqfp package diagram
z89223/273/323/373 zilog 16-bit digital signal processors with a/d converter ds000202-dsp0599 59 ordering information for fast results, contact your local zilog sales office for assistance in ordering the part required. codes package type rom otp 44-pin plcc z8922320vsc z8927320vsc z8922320vec 44-pin pqfp z8922320fsc z8922320fec 64-pin tqfp z8932320asc Z8937320ASC z8932320aec 68-pin plcc z8932320vsc z8937320vsc z8932320vec 80-pin pqfp z8932320fsc z8937320fsc z8932320fec package v = plcc a = tqfp f = pqfp temperature s = 0c to +70c e = C40c to 85c speed 20 = 20 mhz environmental c = plastic standard example: z 89323 20 v s c environmental flow temperature package speed/bond out option product number zilog prefix is a z89323, 20 mhz, plcc, 0c to +70c, plastic standard flow
z89223/273/323/373 16-bit digital signal processors with a/d converter zilog 60 ds000202-dsp0599 ?1999 by zilog, inc. all rights reserved. information in this publication concerning the devices, applications, or technology described is intended to suggest possible uses and may be superseded. zilog, inc. does not assume liability for or provide a representation of accuracy of the information, devices, or technology described in this document. zilog also does not assume liability for intellectual property infringement related in any manner to use of information, devices, or technology described herein or otherwise. except with the express written approval of zilog, use of information, devices, or technology as critical components of life support systems is not authorized. no licenses are conveyed, implicitly or otherwise, by this document under any intellectual property rights. zilog, inc. 910 east hamilton avenue, suite 110 campbell, ca 95008 telephone (408) 558-8500 fax (408) 558-8300 internet: http://www.zilog.com

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